Robert Patti, chief technology officer of Tezzaron Semiconductor Corporation, said at the 3-D Architectures for Semiconductor Integration and Packaging event held in Burlingame, California, that, as part of its attempts at improving performance, Tezzaron Semiconductor has formed an alliance with the R&D foundrySVTC Technologies Incorporated.

At the same time, Robert Patti added, Tezzaron Semiconductor continues to work with Chartered Semiconductor Manufacturing Private Limited, its original foundry partner. In addition, Tezzaron is working with 3 other fab partners, which Patti did not identify.

Robert Patti announced at the 3-D Architectures for Semiconductor Integration and Packaging event that Tezzaron Semiconductor is developing new 3-D devices – including a 4-gigabit DRAM product. This 100-nm product is a discrete part, which attaches, or bonds, to another part, such as a baseband device, or a processor.

For many years now, Tezzaron Semiconductor has been developing high-speed memory products that are based on TSV processes and 3-D wafer stacking. The company claims that its FaStack technology is meant to create 3-D chips – with the core of this process being a tungsten process and a wafer-level stacking.

In this process, device circuitry is divided into many sections, which are built onto separate wafers by using standard processing. Then the wafers are post-processed for thru-silicon interconnection – thus creating hundreds of thousands of vertical ‘Super-Via’ connectors. Later, the wafers are aligned, bonded, thinned, and then diced into individual devices.