The company said it will sample the chips in third quarter of 2010, and start mass production in the fourth quarter of 2010.

Tabula said in a statement that its Spacetime architecture is re-used at multi-gigahertz rates by the dynamic reconfiguration of logic, interconnection and memory in order to provide a density, cost, or power consumption advantage over conventional FPGAs.

This approach, Tabula added, is similar to that of Silicon Basis Limited, headquartered in Bristol, England.

The ABAX products that Tabula will release initially include A1EC02, A1EC03, A1EC04, and the A1EC06 with between 220,000 and 630,000 look-up tables per device. All the 4 parts will have 5.5-Mbytes of RAM, 920 parallel I/Os as well as 44 PLLs. The A1EC06 will have 1,280 multiplier-accumulator blocks.

According to the company, the ABAX devices, designed for an array of applications, will initially target the telecom, wireless infrastructure, and enterprise sectors, All the initial devices in the family will consist of 48 serial transceivers, operating at between 55 Mbits and 6.5 Gbits.

ABAX devices – implemented in a 40-nm process from the foundry TSMC – support a range of soft IP cores, including PCI Express, DDR2 and DDR3 memory controllers, soft CPUs, sRIO, Gigabit and 10 Gigabit Ethernet, OBSAI, and CPRI.