BANGALORE, INDIA: The Power Forward Initiative (PFI) has announced an online publication of “A Practical Guide to Low-Power Design – User experience with CPF.”

The guide captures thousands of hours of actual design experience from many of the 26 PFI-member companies across a variety of low-power designs and products. The guide provides detailed examples of fast, efficient, optimized low-power design using the Silicon Integration Initiative (Si2)-standard Common Power Format (CPF) in a holistic low-power design environment. The guide is now available for viewing and free download.

“Members of the Power Forward Initiative have been using the Common Power Format in some of the industry’s most challenging design projects for more than a year, in some cases nearly two years,” said Steve Schulz, president and CEO of Si2. “A wealth of practical understanding has been gained from this experience, and much of that knowledge was incorporated into revisions of CPF leading up to v1.0.  Now, that know-how has been encapsulated in the form of a user guide that provides step-by-step insight into actual use of advanced low-power design methodologies across various stages of the design flow.”

“This comprehensive guide for integrated circuit (IC) designers represents the collective learning of the companies in the Power Forward Initiative. They have helped shape the CPF specification and have applied it in advanced low-power design flows over the past two years,” said Pankaj Mayor, group director of Business Enablement at Cadence Design Systems, Inc. “The guide will be invaluable to engineers who wish to efficiently achieve the best possible power savings with minimal learning curve.”

“As low power has become the common denominator across all design applications, Virage Logic, the semiconductor industry’s trusted IP partner, recognized the need for a holistic low-power design methodology. To advance the low-power ecosystem, Virage Logic is actively participating in the PFI and is providing support for CPF in our IP,” said Sabina Burns, vice president of corporate marketing at Virage Logic. “With the delivery of ‘A Practical Guide to Low-Power Design,’ the PFI has reached a significant milestone in documenting successful deployment of low-power methodology with CPF.”

Included in the download is a foreword from industry luminary Dr. Alberto Sangiovanni-Vincentelli, an introduction by Cadence CPF architect Dr. Chi-Ping Hsu, and interesting low-power design examples from PFI member companies.  The guide will be continuously updated with more examples throughout 2008.

Cadence contributed the Common Power Format to Si2 in 2006. The contribution was made possible through comprehensive review of CPF by PFI advisors, who provided more than 500 inputs that were subsequently incorporated into CPF.  The new low-power design guide extends the usefulness of CPF with proven methodology and detailed information on specific design experiences. Since its standardization by the Si2 Low-Power Coalition in early 2007, CPF has been used successfully in over 50 production-proven low-power designs worldwide.

The PFI advisory group is comprised of leaders representing all segments of the electronics industry including semiconductor, foundry, semiconductor-equipment, systems and electronic-design automation companies. The extent of participation by these companies attests to the comprehensive applicability of CPF to a wide range of low-power design requirements.