INTEL IDF, TAIPEI, TAIWAN: Providing an overview of the Nehalem processor, at the recently held IDF, Steve Pawlowski, Intel Senior Fellow and CTO, Digital Enterprise Group General Manager, Architecture and Planning, Intel, said that the Nehalem design goals are based on Intel's tick-tock development model.

The Nehalem had three primary goals: multi threads, usage of existing and emerging applications and dynamically scaled performance when needed to maximize enrgy efficiency.

The Nehalem processor was designed for modularity, he said. It was designed keeping the end user in mind, in order to provide energy efficient performance with power efficiency at all levels: from circuit to architecture.

Nehalem delivers high performance and energy efficiency. It is enabled by the co-optimization of all ingredients, such as the Intel QPI or the QuickPath Interconnect Architecture, hyper threading, enhanced cache subsystem, NUMA (non-uniform memory access), fast unaligne cache access and enhanced Macro Fusion, as well as power management: power gates and Turbo Boost technology.

Nehalem Microarchitecture technical disclosures:
* Turbo Boost Technology: In response to workload demand, adds higher speed to active cores.
* Power Gates: Enabled by Intel in-house design and process technology; turns individual cores on/off; transparent to OS; ultra low leakage and cores can run at independent voltage or frequency.
* Hyper-Threading Technology: New and improved with more processor resources.
* Over 3X increase in memory bandwidth.