BANGALORE, INDIA: In every application, power management must take precedence, whether to reduce energy use or to minimize heat dissipation to lower cooling and packaging costs. Power management is becoming an increasingly urgent problem for almost every category of design, as power density, measured in watts per square millimeter, rises at an alarming rate.

From a chip-engineering perspective, effective energy management for a SoC (System-on-a-chip) must be built into the design starting at the architecture stage; and low-power techniques need to be employed at every stage of the design, from RTL (Register Transfer Level) to GDSII.

Power needs to be considered at the very early stages of a design, when the opportunity to save power is at a maximum. At the same time, making a design extremely power efficient results in trading off area and/or timing. A balanced approach is warranted when it comes to power optimization that spans across the entire RTL-to-GDS flow.

Power issues at smaller process geometries
Power consumption grows exponentially at 90nm and beyond technologies. At smaller geometries, aggressive management of leakage current can greatly impact design and implementation choices. Indeed, for some designs and libraries, leakage current exceeds switching currents, thus becoming the primary source of power dissipation in CMOS, as shown in Fig 1.

Voltage cannot scale indefinitely, and capacitance (dominated by more wires with higher wire capacitance) increases, while frequency keeps going up. Ineffective power management causes decreased battery life, lower chip performance, increases area due to cooling needs, or simply makes the design non-functional.

'Power Aware' designs
Two aspects of “power awareness” are essential for effective designs that minimize power consumption—the level of abstraction, and Quality of Silicon (QoS). The higher the level of abstraction when power is taken into account, the greater the power efficiency that can be gained, because there is more freedom to make large changes to the design implementation.

New system and architecture designs can yield implementations that are 10 to 20 times more power efficient than previous designs, so optimization and analysis of power early in the design process, at high levels of abstraction, are critical (see Fig. 2).

QoS is becoming the new standard for evaluation of the “goodness” of an IC design, because this measurement requires placement and routed wires that account for the majority of the timing equation in nanometer designs. QoS measurements include speed (timing of the performance limiting paths), die area, and power. The power portion of QoS measurements consists of the static and dynamic power consumption determined using real wires.

As QoS is fast becoming the metric for an entire design, a holistic set of tools is required so designers can gain a better understanding of power/area/performance tradeoffs, and come up with the most effective balance for each individual design.

To achieve required power targets, design teams must adopt advanced power management techniques such as multi-supply multi-voltage (MSMV), dynamic voltage and frequency scaling (DVFS), and power shutoff (PSO). Such techniques, however, increase design complexity and introduce risk.

Conventional design flows fail to address the additional considerations for incorporating advanced low-power design techniques. Consequently, design teams often resort to ad hoc or inflexible methodologies that result in lower productivity, increased risk of silicon failure, longer time to market, and inferior product performance.

Power Forward Initiative and Common Power Format
To facilitate and support a new era of low-power design innovation, Cadence has formed the Power Forward Initiative. 

Drawing from the collective expertise of leading technology companies, the Power Forward Initiative will create a more systematic, integrated approach to low-power design, providing a platform for higher-level exploration and IP reuse.

Power Forward Initiative members are already at work on validating the Common Power Format (CPF), a new open specification language that captures all power-specific design, constraint, and functionality requirements, such as multi-supply voltage and power shutoff, in a single file.

By linking design, verification, and implementation domains, the Common Power Format enables automation of power-reduction techniques and increases predictability. No longer constrained by the risk of low yield or costly re-spins, design teams can focus their time and resources on what matters most: innovation. Achieving both functional and structural verification before incurring manufacturing costs, and with greater time-to-market opportunities, companies across the design and manufacturing chain can adopt new process geometries and start low-power design projects profitably.

The author is Product Marketing Manager, Cadence Design Systems (I) Pvt Ltd