SAN JOSE, USA: Cadence Design Systems Inc. has introduced  the Cadence C-to-Silicon Compiler, a high-level synthesis product that improves designer productivity up to 10 times in creating and re-using system-on-chip IP.

The innovative technology in C-to-Silicon Compiler helps bridge the gap between register transfer level (RTL) models, commonly used to verify, implement, and integrate SoCs, and system-level models, usually written in C/C++ and SystemC.

"Earlier this year Cadence outlined its strategy to expand into the system-level adjacency under a major internal initiative we call 'Sydney,'" said Jim Miller, executive vice president, Products and Technologies Organization, at Cadence. "C-to-Silicon Compiler is the first new product we're delivering as part of that holistic vision to enable customers to reduce iterations between system specification and design implementation and improve designer productivity for IP creation and re-use, which is particularly important in the consumer, wireless, and wired networking market segments."

C-to-Silicon Compiler enables engineers to design at a higher level of abstraction and helps automate the analysis of hardware micro-architecture. Designer productivity is improved because the technology automatically translates and optimizes abstract behavioral descriptions from C/C++ and SystemC to synthesizeable Verilog RTL (including assertions) for implementation, verification and SoC integration.

C-to-Silicon Compiler has two very distinctive capabilities: embedded logic synthesis using Cadence Encounter RTL Compiler global synthesis that ensures high accuracy and high-quality implementation results for designs with mixed control and datapath, and a behavior-structure-timing database that provides the ability to perform true incremental synthesis, for example re-synthesizing only the parts of the design that changed, while leaving the rest untouched.  Finally, to support verification, C-to-Silicon Compiler generates fast cycle-accurate hardware models of the RTL, and supports fast mapping to RTL verification with Incisive simulation and Palladium/Xtreme emulation-acceleration products.

The C-to-Silicon Compiler technology was developed with significant input from customers, such as Hitachi and Renesas, who are developing IC products starting with system-level IP.

"From the early stage, Renesas has been evaluating C-to-Silicon Compiler and providing extensive guidance to Cadence in its development," said Hisaharu Miwa, general manager of Design Technology Div., LSI Product Technology Unit, Renesas Technology Corp. "We have found that C-to-Silicon Compiler improves significantly upon the existing RTL base design flow, and we recently applied it to several new IP designs, with significant productivity gains for Renesas engineers."

"Hitachi has partnered with Cadence on the development of C-to-Silicon Compiler for more than two years, and we are very pleased with the results," said Teruhisa Shimizu, center manager of Design Platform Center, MONOZUKURI Innovation Operation, Hardware MONOZUKURI Division at Hitachi, Ltd. "We are now planning to use C-to-Silicon Compiler in several production designs. The machine-generated RTL is equal to or better than the RTL generated manually, but with much less effort. We anticipate this new technology will substantially increase productivity and quality improvement in developing new System design at Hitachi."

Matt Volckmann, senior analyst/program manager within Venture Development Corporation's Embedded Software Practice, said, "With the announcement of C-to-Silicon Compiler, Cadence is well-positioned to expand its presence in the system-level verification domain into the system design domain."

The Cadence C-to-Silicon Compiler is available now in limited production. C-to-Silicon Compiler will be demonstrated during the DA SHOW/CDNLive! conference starting July 17.