Arteris FlexNoC IP collaborates with Synopsys Platform

Arteris FlexNoC IP collaborates with Synopsys' Platform

The collaboration enables model of Arteris' FlexNoC interconnect IP to be used with Synopsys' Platform Architect environment, offering system designers the ability to simulate realistic system-level performance of their end product architectures

Thursday, February 16, 2012

MOUNTAIN VIEW, USA: A provider of software and IP services Synopsys, Inc and Arteris Inc., provider of network-on-chip (NoC) interconnect IP solutions, recently announced a collaboration that enables models of Arteris' FlexNoC interconnect IP to be used with Synopsys' Platform Architect environment, offering system designers the ability to simulate realistic system-level performance of their end product architectures.

SystemC transaction-level models (TLMs) generated by Arteris' FlexNoC configuration tool can now be easily united with Synopsys' architecture design models and traffic generators, enabling early analysis of end-application performance, and highly efficient optimization of multicore system architectures months before system software or register transistor language (RTL) designs are available, said a press release.

With newly enhanced transactors and analysis monitor support for Arteris' FlexNoC interconnect models, Synopsys' Platform Architect environment with Multicore Optimization Technology (MCO) offers system architects three distinct advantages for early performance analysis and optimization of complex designs:

1) obtaining fully-instrumented performance models before software and RTL availability

2) clearly measuring and visualizing the dynamic behavior and performance bottlenecks of multicore designs
3) automating the design flow to enable developers to explore hundreds of architecture alternatives in days versus weeks or months with paper specifications and RTL methods.

"Arteris FlexNoC's integration with Synopsys' Platform Architect MCO environment allows our customers to create better SoCs in less time," said K. Charles Janac, president and CEO of Arteris.

He added that the integration of the two technologies allows SoC designers to have the same quick turn-around simulation times they experience today with FlexNoC, while gaining critical benefits from the more realistic simulation and earlier analysis of their application scenarios.

Arteris FlexNoC's silicon-proven commercial network-on-chip interconnect IP offers the ability to reduce the number of interconnect wires and logic required for multicore SoC design. Reducing the interconnect wires and logic gates resolves routing congestion and timing closure issues at the back-end place-and-route stage, resulting in shorter development cycle time, faster SoC frequencies, smaller SoC area and less SoC power.

"Our goal is to help system designers and architects avoid late discovery of system performance problems that can be extremely costly for both project schedules and budgets. By starting architecture analysis and optimization at the transaction-level with Arteris' FlexNoC interconnect models in Synopsys' Platform Architect MCO, we offer SoC architects the ability to perform accurate simulation of the multicore system and its most critical application use-cases earlier," said John Koeter, vice president of marketing for IP and systems at Synopsys.

He added that with this combination they could achieve the best balance of performance, power and cost at a time in the development process where they have the greatest impact.

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