The project – codenamed SOLID (Silicon printing Optimisation with Lithography control and Integrated Design) – is meant to optimise the patterning process from design to manufacturing as well as to extend characterisation tools and methods to develop new compensation and correction techniques for cutting variability.

The SOLID project, ASML Holding said in a press release, is also targeted at exploring lithography options for making complex chips at sub-30-nm nodes.

According to Joel Hartmann, director of silicon technology development at STMicroelectronics, based in Crolles, France, STMicroelectronics has decided to work with Tachyon SMO source-mask co-optimisation, from Brion Technologies (which is a subsidiary of ASML Holding) and also in collaboration with the illumination sources of ASML.

STMicroelectronics already has used the Tachyon optical proximity correction and lithography manufacturability check software of Brion Technologies for its 45-nm production.

According to Joel Hartmann, the joint development project – combined with ASML Holding’s integrated suite of lithography products – offers STMicroelectronics the computational and wafer lithography technologies, which would enable the company to develop optimum manufacturing solutions at 28-nm and below.

Hartmann described the joint venture as a “perfect example” of a project that is developed within the framework of the Nano2012 program.

Led by STMicroelectronics, the Nano2012 is a strategic R&D program which gathers research institutes as well as industrial partners. The program is supported by the national, regional and local authorities of France – with the total funding amounting to about 450 million euros (around $680 million).