WILSONVILLE, USA: Mentor Graphics Corp. recently announced that Dr. Janusz Rajski has been named an IEEE Fellow.

Dr. Rajski is being recognized for contributions to digital VLSI circuit testing and test compression. His innovations have enabled the IC industry to keep the cost of testing digital circuits almost constant over a ten year period when the complexity of ICs has expanded exponentially according to Moore’s Law, said a press release.

The IEEE Grade of Fellow is conferred by the IEEE Board of Directors upon a person with an outstanding record of accomplishments in any of the IEEE fields of interest.

The total number selected in any one year cannot exceed one-tenth of one-percent of the total voting membership. IEEE Fellow is the highest grade of membership and is recognized by the technical community as a prestigious honor and an important career achievement. In 2011, 321 individuals have been elevated to IEEE Fellow, the release added.

In 2002, Dr. Rajski published his first contribution on the Embedded Deterministic Test (EDT) technique. This method compresses test patterns before they are applied by automatic test equipment (ATE), and uses a small amount of logic in the IC under test to expand the patterns during the test process.

The process is reversed to extract test results. This approach has achieved compression ratios of over 100X, greatly reducing the time required to test an IC, and also reducing the cost of the ATE itself, without reducing test coverage or quality.

EDT technology is a critical component of the market leading Mentor Tessent TestKompress product line for high quality, low cost IC testing, which won the Best in Test award in 2001 and the Test of Time award in 2009 from Test and Measurement World magazine.