Mentor on key EDA trends ESL and solar/PV

EDA

Mentor on key EDA trends, ESL and solar/PV

System level design and IC implementation are development stages where there are the most challenges, and therefore, the most opportunities

Pradeep

Thursday, September 25, 2008

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BANGALORE, INDIA: There have been whispers that the EDA industry has been lagging behind semiconductors and is in the catch-up mode. Continuing my discussion with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics, we touched upon this aspect, as well as the role of ESL and DFM as growth drivers, and of course, a possible role for EDA/EDA tools in solar/PV. Excerpts:

CIOL: EDA is said to be lagging behind the semiconductor industry at the moment, and is in the catch-up mode. What is your opinion?

Joseph Sawicki: That’s a matter of perspective. There are definitely unsolved challenges at 32nm and 22nm, but the reality is that we are still in the technology development stage. For EDA tools that address implementation and manufacturing issues (i.e., Mentor design-to-silicon products), there are dependencies that cannot be fully resolved until the process technology has stabilized.

Mentor Graphics is laying the groundwork for those challenges and working in concert with the process technology leaders to ensure that our products address all issues and are production-worthy before the process technology goes mainstream.

On the other hand, although Mentor’s products are fully-qualified for 45nm, there have only been a handful of tapeouts at that node, so for the majority of customers, we are ahead of the curve.

CIOL: Would you agree that ESL and DFM are the growth drivers and why?

JS: As Wally Rhines has said in his public presentations, system level design and IC implementation are the stages of development where there are the most challenges, and therefore, the most opportunities.

To continue the traditional grow spiral that the electronic industry has enjoyed as a result of device scaling, we need more sophisticated EDA solutions to deal with both of these challenges.

ESL is responding to the growth of design complexity and the need for earlier and more thorough design verification, including low power characteristics, and software integration.

The Design-to-Silicon division is addressing the issues of IC implementation which result not only from the increase in design complexity and devices sizes, but also from increasing sensitivity of the manufacturing process to physical design decisions, a phenomenon often referred to as “manufacturing variability.”

Although the term “Design-For-Manufacturing” reflects the need to consider manufacturability in design and to optimize for both functional and parametric yield, it is important to emphasize that DFM is not simply an additional tool or discrete step in the design process, but rather an integration of manufacturing process information throughout the IC implementation flow.

CIOL: EDA is starting to move up to the system level. Will this make it less dependent on semiconductor world. Comments?

JS: As stated in response to the earlier, question, there are challenges at both the front end and back end of the electronic products design and manufacturing life cycle. Both of these opportunities are growing.

In addition, developments like multi-level (3D) die packaging, through-silicon via (TSV) structures and other non-traditional techniques for device scaling are pushing system and silicon design issues closer together.

Reaching the 22nm node will require highly compute intensive EDA techniques for physical design to compensate for limitations in the manufacturing process. Beyond that, we could see a major shift to new materials and manufacturing techniques that would open new green fields for EDA in the IC implementation flow.

CIOL: With single threading, we can no longer handle designs over 100 million gates. Of course, at 45nm, you can do a 100mn gates. That rewriting process is another issue that is also slowing out. How is Mentor handling this?

JS: Mentor has incorporated sophisticated multi-threading and multi-processing technologies into all of its performance-sensitive applications, from place-and-route, through physical verification, resolution enhancement and testing. Our tools have a track record of impressive and consistent and performance and scalability improvements, which is why we continue to lead the industry in performance.

In addition to merely adding multi-threading and support for multi-core processors, Calibre products have a robust workflow management environment that automatically distributes the processing workload in the most efficient manner across any number of available clustered computing nodes.

The Olympus-SoC place-and-route is inherently scalable due to its advanced architecture which includes an extremely efficient graph representation for timing information, and a very concise memory footprint. In addition, all the engines within Olympus-SoC can take advantage of multi-threaded and multi-core processors for high performance. These features enable Olympus-SoC to handle 100M+ gates designs in flat mode without excessive turnaround time.

Mentor’s ATPG tools also are designed to operate in multiprocessing mode over multiple computing platforms to reduce test pattern generation time. In addition, Mentor test pattern compression technology reduces test pattern volume and test time, making it feasible to fully test 100M gate devices and maintain product quality without an explosion in test cost.

CIOL: How do you see the EDA industry evolving, going forward?

JS: There are three key trends to watch. Firstly, for design to remain affordable at the leading edge, we need to enable radical increases in productivity. Electronic System Level (ESL) design is the key here, allowing designers to move to a new level of abstraction for both design and verification.

Secondly, the challenges of manufacturing a well-yielding and reliable device as we move to 22nm will require a far more sophisticated physical implementation environment—one that accounts for physical effects in the design loop, and accounts for manufacturing variability in it's optimization routines.

Finally, the manufacturing challenges also open significant opportunity for EDA in the manufacturing space. A great example of this is the September 17, 2008 announcement we did with IBM on a joint development program to enable manufacturing at the 22nm node.

CIOL: Is there an opportunity for EDA in solar/PV?

JS: Because photovoltaic devices have very simple and regular structures, most of the opportunity for EDA is not in logic design tools, but in material science, transistor-level device modeling, and manufacturing efficiencies with a focus on conversion efficiency and manufacturing cost reduction.

EDA's role in solar will be in the newer areas related to Design-for-Manufacturing and other manufacturing optimizations.

The last part of this discussion will feature this weekend.

©CIOL Bureau

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