Synopsys delivers 2X speed-up with IC compiler

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Synopsys delivers 2X speed-up with IC compiler

Faster runtime, enhanced design closure, and increased automation boost designer productivity

Tuesday, September 30, 2008

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MOUNTAIN VIEW, USA: Synopsys Inc. announced the availability of IC Compiler 2008.09, delivering a dramatic boost in IC designer productivity. The latest release features faster runtimes across the board, leading to a 2X to 3X speed-up in overall turnaround time.

This release also introduces new technology that speeds design closure including improved timing, variation-aware clock-tree synthesis, lower power, enhanced DFM, and signoff-quality incremental design-rule checking. With this release, the recently-announced Zroute technology delivering a 10-fold speed-up in routing is now available as a standard feature to all IC Compiler customers.

"We have seen 2X to-3X improvements in turn-around time with our current release of IC Compiler on some of our multi-voltage designs," says Danny Merchant, senior director of Corporate CAD from Cypress Semiconductor Corp. "With the latest advances in IC Compiler 2008.09, we expect further performance improvements and look forward to a faster production flow."

Compared to the prior release (2007.03), the new IC Compiler 2008.09 release has demonstrated an average speed-up of 2X across a broad set of customer designs. A total of 3X speed-up may be achieved by enabling multi- threading on quad-core machines that are commonly used in the IC Compiler customer base.

Synopsys has observed even higher speed-up in select customer cases through methodology review and optimization. Key technologies leading to the increase in speed include enhanced placement optimization, faster signal-integrity closure and hold-time fixing, faster multi-corner/multi-mode, improvements in multi-threaded placement and the newly-released Zroute technology.

IC Compiler 2008.09 further speeds up design closure by introducing a number of new and enhanced technologies. Clock tree synthesis now includes concurrent multi-corner optimization and new low-power techniques. A new clock-mesh capability is included to generate variation-tolerant clock structures. New DFM capabilities include via-minimization, redundant via optimization and lithography-friendly routing. Signoff quality design-rule-checking using foundry run-sets can now be invoked from inside IC Compiler to perform incremental area-based checking, helping reduce turnaround time from hours to minutes.

"Aggressive technology innovations along with differentiated results have helped IC Compiler become the technology-leading product in the place-and-route market," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "Speeding up turnaround time has been a key target for us, and IC Compiler 2008.09 delivers a major installment towards this target. Our customers can expect to fruitfully leverage the new capabilities across all of their applications."

IC Compiler 2008.09 is available to all current customers now. The release includes a quad-core license of Zroute technology as a standard feature. Many of the enhancements in 2008.09 are also available in the latest service-pack of the current release for those customers who are unable to immediately consider a platform change.

©CIOL Bureau

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