BANGALORE, INDIA: Designers today continue to be challenged with the need to manage power, timing and signal integrity concurrently throughout the design flow and must evolve to enable design for energy efficiency.

Alok Mehrotra, managing director, Magma Design Automation talks to Divya Girish of CIOL about the importance of energy efficient SoC designs in the industry and the new techniques that designers can use to reduce power in today’s ICS.

CIOL: The SoCs today contain both analog and digital elements. For more effective and cost-effective IC implementation, designers need a mixed-signal SoC design environment? Can you comment on this?

Alok Mehrotra: This is very true that SoCs have become the prevalent integrated circuits addressing the compute, communication, consumer and mobile applications. The SoCs contain both digital and analog content and analog design is becoming critically important to semiconductor companies as increasingly product differentiation resides in the analog functions. For efficient and cost-effective SoC implementation, it is imperative to have a good mixed-signal design environment. But analog design flows have changed little for decades.

Analog design is often a critical bottleneck in the chip design process with design corner exploration requiring massive iterations in simulation to converge. Design of analog derivatives requires extensive redesign, with little analog reuse and migration of analog designs to new processes takes prohibitive time and resources. The layout effects at small geometries forces much iteration between circuit design and layout.

The Titan Accelerators of Magma deliver huge value to semiconductor companies by augmenting their analog flows to improve analog design productivity and enable analog design reuse. The Titan Mixed-Signal Design Platform is the first full-chip mixed-signal design environment. Titan tightly integrates analog implementation and verification while delivering first-time-correct, predictable mixed-signal designs. Unlike other design solutions, Titan also integrates digital implementation providing a quantum leap in efficiency for mixed-signal chip development.

CIOL: Can you elaborate on the importance of energy efficient SoC designs in the industry and the new techniques that designers could use to reduce power in today’s IC?

AM: Designers today continue to be challenged with the need to reduce power for their SoCs targeted to mobile applications. Traditional power optimization techniques are effective but insufficient to achieve the targeted energy efficiency.
New techniques achieve dynamic power reduction through activity driven clock gating and physically aware optimization. The Chill product of Magma performs activity driven combinatorial and sequential clock gate optimization. This power-aware netlist optimization results in dynamic power reduction of up to 20 per cent on power optimized designs.