Synopsys DesignWare IP for PCI Express

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Synopsys DesignWare IP for PCI Express

It has been used as the Gold Standard in Intel Lab at Intel Developer Forum

Monday, August 18, 2008

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MOUNTAIN VIEW, USA: Synopsys Inc. announced that Synopsys' DesignWare IP for PCI Express with PCI-SIG I/O Virtualization (IOV) technology has completed testing at Intel's labs and will be used as the gold standard to demonstrate single root IOV (SR-IOV) running on the latest Intel hardware platforms at the Intel Developer Forum (IDF).

The silicon-proven DesignWare digital controller and PHY IP for PCI Express with PCI-SIG IOV technology has been thoroughly tested using Intel's SR-IOV hardware platforms and Independent Hardware Vendor (IHV) test software, demonstrating that the IP is interoperable and functions in accordance to the PCI-SIG IOV specification.

Proven interoperability of the DesignWare IP for PCI Express allows designers to lower the risk of integrating PCI-SIG IOV technology into their system-on-chips (SoCs) and helps speed adoption of the standard.

"Demonstrating interoperability between the DesignWare IP for PCI Express with Intel's hardware platform is an example of how Synopsys continues to actively promote and support the latest industry standards," said John Koeter, Vice President of Marketing for IP and Services at Synopsys. "As a leader in PCI Express IP, we provide proven, interoperable and high quality IP for SR- IOV, which helps designers quickly deliver differentiated blades, servers and storage systems to the market."

"SR-IOV is a key technology that is being driven for enterprise computing customers to lower costs and increase performance of virtualized systems," said Jim Pappas, Director of Initiative Marketing for Intel. "By working closely with leading technology companies such as Synopsys, Intel is contributing to an ecosystem that consists of the latest tools, IP and platforms that support the PCI-SIG IOV technology."

The Synopsys hardware used in the labs at IDF consists of DesignWare digital controllers and PHY IP for PCI Express, which fully support the PCI- SIG SR-IOV 1.0 specification. The DesignWare IP solution for PCI Express with IOV technology supports multiple Physical Functions (PF) and Virtual Functions (VF) such as Alternative Routing ID Interpretation (ARI), Function Level Reset (FLR), and Address Translation Services (ATS), providing designers with the ability to select the optimal feature set required for their target design. Synopsys will also be demonstrating the digital controllers and PHY IP in the PCI Express Technology Community Booth #726.

The comprehensive DesignWare IP for PCI Express solution with support for PCI-SIG SR-IOV is available now.

©CIOL Bureau

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