SAN JOSE, USA & BANGALORE, INDIA: Cadence Design Systems Inc. recently announced the C-to-Silicon Compiler, which is said to be the next-generation of HLS (high-level synthesis) technology. It eliminates historical barriers to HLS adoption and delivers the quality of results and net productivity gains that engineers need.

The C-to-Silicon Compiler produces RTL (register transfer level) with quality at or above the 90th percentile of manual RTL design, while increasing engineering productivity up to 10X. HLS reduces manual effort required to produce RTL, and enables designers to avoid syntax errors common in traditional methodologies.

First  up, what will this product actually do for the EDA industry? According to Steve Svoboda, marketing director for system level design products, Cadence Design Systems, this product can actually take EDA to a new level in terms of delivering additional productivity to designers.

"When design compiler and logic synthesis came, it was during the golden era of the semiconductor industry. Productivity was increasing rapidly. But the problem is, since the early 1990s, there has been no real change in the RTL design methodology. The only productivity increase has come out in form of design re-use," he says.

"This (C-2-Silicon Compiler) could re-energize semiconductor and EDA industries by at least 10X times. About 20 years ago, there was 10X productivity increase. By having HLS, we can now close the gap and tackle the chips more effectively now," he contends.

Manual RTL coding not efficient
In IC design, the RTL is a way of describing the operation of a digital circuit. In RTL design, a circuit's behavior is defined in terms of the flow of signals (or transfer of data) between hardware registers, and the logical operations performed on those signals.
 
RTL abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived. Currently, verification engineers have to write RTL code manually using Verilog or VHDL languages. This method has been the norm for over 15 years now. While it was revolutionary when first introduced, with the current complexity of chips, this type of manual RTL coding is not efficient. It can lead to mistakes and is time consuming!
 
The hard reality is that (until now) HLS (high-level synthesis) tools have been unable to deliver the quality of results (QoR) and expected net productivity gains to justify broad adoption. For the most part, RTL developers work much the same way today, as they did in the early 1990's, except that today's IC designs are 50x to 100x larger and more complex.
 
C, C++ and SystemC are languages that are more flexible and easier to use for coding algorithms and doing any kind of architecture exploration than Verilog or VHDL. Currently, designers use C and SystemC for architectural exploration, but finally implementing the algorithm manually in Verilog/VHDL languages. In effect, they are designing twice, once in C, and then in Verilog for the RTL. Clearly, this is inefficient, time consuming and can lead to errors. That's where Cadence's C-to-Silicon Compiler comes in!